The Viterbi Decoder is used in any modern communication system such as GSM (k=5),
WLAN (k=7), IS-95, CDMA, DAB-DVB, 3G (k=9) or HDSL2 (k=10).
The Viterbi Decoder Toolbox can generate the Verilog RTL code
and the testbench for the choosen configuration.
The IP core is a customization for combined DAB/DMB & DVB convolutional FEC applications,
sharing the same Add-Compare-Select module, for both coding rates.
The Toolbox can generate the Verilog RTL code and the testbench for the choosen configuration
(note: the soft decisions are available only for QPSK modulation; BPSK, M-QAM can used as well).
The combination of the convolutional coding and modulation scheme,
known as Trellis-Coded Modulation (TCM),
can achieve significant coding gain
without reducing the data rate or requiring more bandwidth.
The Finite Impulse Response filter is used in many DSP applications in a variety of characteristics and implementations. Using a toolbox to generate the HDL and simulation files can greatly improve the productivity and reduce the design time.
The multiplier is an important aspect for DSP algorithms and in many cases
the use of a multiplier can't be avoided. The Signed Multiplier RTL Code Generator toolbox
can generate the Verilog RTL code for the selected configuration.