Home page
  Home  |  Contact  |  Login
 IP Cores   Matlab Toolboxes   Design Services   
Home :: Integrated Circuits :: IP Cores
IP Cores
 Viterbi Decoder IP Core
 Product code: VDEC06
The Viterbi Decoder is used in any modern communication system such as GSM (k=5), WLAN (k=7), IS-95, CDMA, DAB-DVB, 3G (k=9) or HDSL2 (k=10). The Viterbi Decoder Toolbox can generate the Verilog RTL code and the testbench for the choosen configuration.
 DAB-DMB-DVB Viterbi Decoder IP Core
 Product code: DAB-DVB-VD01
The IP core is a customization for combined DAB/DMB & DVB convolutional FEC applications, sharing the same Add-Compare-Select module, for both coding rates. The Toolbox can generate the Verilog RTL code and the testbench for the choosen configuration (note: the soft decisions are available only for QPSK modulation; BPSK, M-QAM can used as well).
 TCM Decoder IP Core
 Product code: TDEC01
The combination of the convolutional coding and modulation scheme, known as Trellis-Coded Modulation (TCM), can achieve significant coding gain without reducing the data rate or requiring more bandwidth.
 CORDIC Processor IP Core
 Product code: COR01
The CORDIC Processor IP Core can replace large cosine & sine LUTs and also can be used for complicate mathematical functions decompositon into simple shifts and additions operations.
 Complex LMS Adaptive Filter IP Core
 Product code: CAF02
The LMS Adaptive Filter IP Core can be used in a communication system with modulation up to 1024-QAM.
 FIR Filter IP Core
 Product code: FIR01
The Finite Impulse Response filter is used in many DSP applications in a variety of characteristics and implementations. Using a toolbox to generate the HDL and simulation files can greatly improve the productivity and reduce the design time.
 Signed Multiplier IP Core
 Product code: MULT-SGN01
The multiplier is an important aspect for DSP algorithms and in many cases the use of a multiplier can't be avoided. The Signed Multiplier RTL Code Generator toolbox can generate the Verilog RTL code for the selected configuration.
  Legal information  |  Privacy policy  
  Copyright 2003-2005, Integrated Circuits and Software Design SRL. All Rights Reserved.   Last update: