When the project schedules are tight and also the developments budget must be met, we can provide you custom IP cores together with the verification environment, based on Modelsim.
The Modelsim testbench can be accompanied with Matlab scripts or GUIs to check the performances of the HDL implementation.
Also, we can offer you the tools to verify your mathematical model in the form of Matlab scripts or GUIs.
ICS Design offers the following services:
Custom IP core development
Design and debugging for FPGA/ASIC based projects
Modelsim testbenches for functional or gate-level simulations
Matlab model development for the requested IP core
Verilog RTL code generators, testbench code generators (Matlab or Visual Basic)