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DAB-DMB-DVB Viterbi Decoder IP Core (DAB-DVB-VD01)

    The IP core is a customization for combined DAB/DMB & DVB convolutional FEC applications, sharing the same Add-Compare-Select module, for both coding rates. The Toolbox can generate the Verilog RTL code and the testbench for the choosen configuration (note: the soft decisions are available only for QPSK modulation; BPSK, M-QAM can used as well).
     The simulation can use different channel models: AWGN, ISI (raised cosine) and flat fading (Rayleigh or Rician pdf).
    For decoding the 4-pointers trace-back method is implemented and the survivor memory length is parameterizable, according with performance required. A good performance is given by the merge memory length which is half of the total survivor memory. The decoding latency is four times reduced by using the 4-pointer decoding scheme.
    In the Add-Select-Compare Unit the normalization for the accumulated path metrics can be used.
    The trace-back process is controlled by Finite State Machines. The packet length (in bits) is an input to the core.
    The input soft decisions can be 3,4,5 or 6 bits wide.
     Full parameterization is also available.
    Below are the test results for AWGN and flat fading Rayleigh channels.
Decoding method: Trace-back
Coding rates: 1/2 (DVB) & 1/4 (DAB/DMB)
4-pointer trace-back decoding method for lower latencies
Soft decisions: starting with 3 bits wide
Code distance: Manhattan or Euclidean (LUT)
Quantization type: signed with null value
Bit errors estimator
Channels: AWGN, ISI or Rayleigh/Rician
Plots using files generated by Verilog simulation
Synthesis Results
Technology K SDec Gates  f [MHz]
ASIC - 0.25 m 7 4 b 82K 180
FPGA - Xilinx 7 4 b 30% xc4vfx12 160
7 4 b 88% xc3s200e 98
Test Results
Technical Support
Complete RTL code generator (p-code, m-code)
PLI user task code for Channel/ADC/QPSK blocks
Price List
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