The Viterbi Decoder is used in any modern communication system such as GSM (k=5),
WLAN (k=7), IS-95, CDMA, DVB, 3G (k=9) or HDSL2 (k=10). The Viterbi Decoder Toolbox can generate the Verilog RTL code
and the testbench for the choosen configuration (note: the soft decisions are available only for QPSK or BPSK modulation).
Can be also used in other communication systems which are using a convolutional encoder with coding rate R=1/2, 1/3 or 1/4.
The simulation can use different channel models: AWGN,
ISI (raised cosine) and multipath (Rayleigh or Rician).
For decoding the 4-pointers trace-back method is implemented
and the survivor memory length is parameterizable, according with performance required.
By example, for WLAN, a good performance is given by the merge memory length of 64 to 128 bits.
The decoding latency is four times reduced by using the 4-pointer decoding scheme.
Also the register-exchange decoding method is available.
In the Add-Select-Compare Unit the modulo normalization or simple normalization
for the accumulated path metrics can be used.
The trace-back process is controlled by 3 finite state machines, these
allowing an input packet length of 20 bits to continuous mode (infinite length).
Hard or soft decisions can be selected as input.
The Toolbox also offers the BER curve for mathematical model.
Features
Flexible decoding: Trace-back or Register Exchange methods
Constraint lengths starting with k=3, rate R=1/2, 1/3 & 1/4
4-pointer trace-back decoding method for lower latencies
Hard / Soft decisions - starting with 3 bits wide
Supports 4-tuple data packets length and continuous mode
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