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FIR Filter IP Core (FIR01)

    The Finite Impulse Response filter is used in many DSP applications in a variety of characteristics and implementations. Using a toolbox to generate the HDL and simulation files can greatly improve the productivity and reduce the design time.
    The FIR FILTER RTL Code Generator toolbox can generate the Verilog RTL code for the selected configuration. Several design options are available, as can be seen in the picture, this allowing an optimal design for the filter. Using up to 6 levels of pipelining the timing can be improved but also the combinational version is available. Based on the resulted filter configuration the toolbox can also generate the complete Verilog Modelsim testbench with 2 typical response tests: impulse and step response. The Amplitude spectrum in dB and the impulse response are plotted in the GUI window and other plots are available in separate windows.
    This toolbox provides a fast way to check at once the silicon implementation of the designed FIR filter.
 
Features
Other Matlab toolboxes not needed
3 transversal filter architecture
Suitable for up to 32 bits coefficients width (TC only)
Real format coefficients converted to binary TC format
MAC: Pipelining up to 6 levels
Carry Propagation or Carry Look-Ahead adders
Verilog RTL code generator
Complete Modelsim testbench generator (TC only)
Plots using files generated by Verilog simulation
Synthesis Results
Technology Type Pipeline levels Gates  f [MHz]
ASIC - 0.25 m 25 Taps Filter
MAC: M12x22 &CLA
6 clks 53k 260
FPGA - Xilinx Virtex 25 Taps Filter
MAC: M12x22 &CLA
6 clks 98% xcv400e 125
 
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