The multiplier is an important aspect for DSP algorithms and in many cases
the use of a multiplier can't be avoided.
The Signed Multiplier RTL Code Generator toolbox can generate the Verilog RTL code for the selected configuration.
Several design options are available, this allowing an optimal design for the multiplier.
Using up to 5 levels of pipelining the timing can be improved but also the combinational version is available.
Based on the resulted multiplier configuration the toolbox can also generate
the complete Verilog Modelsim testbench with 3 typical tests: random inputs and 2 monotonic inputs.
This feature provides a fast way to check at once the silicon implementation of the designed multiplier.
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