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Signed Multiplier IP Core (MULT-SGN01)

    The multiplier is an important aspect for DSP algorithms and in many cases the use of a multiplier can't be avoided. The Signed Multiplier RTL Code Generator toolbox can generate the Verilog RTL code for the selected configuration.
    Several design options are available, this allowing an optimal design for the multiplier. Using up to 5 levels of pipelining the timing can be improved but also the combinational version is available.
    Based on the resulted multiplier configuration the toolbox can also generate the complete Verilog Modelsim testbench with 3 typical tests: random inputs and 2 monotonic inputs. This feature provides a fast way to check at once the silicon implementation of the designed multiplier.
Other Matlab toolboxes not needed
Booth - 2 partial products reduction algorithm
Suitable for up to 32 bits
Carry Propagation or Carry Look-Ahead adders
Modelsim testbench generator (TC only)
Pipelining up to 5 levels
Multiplier configuration information displayed
Synthesis Results
Technology Type Latency Gates  f [MHz]
ASIC - 0.25 m 12x22 CLA 5 clks 3520 305
12x22 CPA 4 clks 3680 250
FPGA - Xilinx Virtex 12x22 CLA 5 clks 45% xcv50e 125
12x22 CPA 4 clks 45 % xcv50e 95
Technical Support
MATLAB p-code under License Agreement terms
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