The CORDIC Processor IP Core can replace large cosine & sine LUTs
and also can be used for complicate mathematical functions decomposition into simple shifts and additions operations.
The Radix-2 CORDIC Processor RTL Code Generator toolbox can generate the Verilog RTL code for the selected configuration.
For an optimal solution to your design requirements several options are available, as can be seen in the picture, such as the architecture,
the type of functions to be implemented and the number of bits used for quantization as well the number of micro-rotations.
The precision of calculations is depending on the level of quantization and number of microrotations.
For example using 24-bit inputs we can exactly match the theoretical precision of the algorithm.
A finite state machine is used to control the processing core.
For a good comparison, the Matlab model it is also provided.
The complete Verilog Modelsim testbench is generated according with options we made.
For every function implemented we can check the output values and trajectories as well the relative errors to the Matlab model.
The toolbox provides a fast way to check at once the silicon implementation of the designed CORDIC Processor.
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