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CORDIC Processor IP Core (COR01)

    The CORDIC Processor IP Core can replace large cosine & sine LUTs and also can be used for complicate mathematical functions decomposition into simple shifts and additions operations.
    The Radix-2 CORDIC Processor RTL Code Generator toolbox can generate the Verilog RTL code for the selected configuration. For an optimal solution to your design requirements several options are available, as can be seen in the picture, such as the architecture, the type of functions to be implemented and the number of bits used for quantization as well the number of micro-rotations.
    The precision of calculations is depending on the level of quantization and number of microrotations. For example using 24-bit inputs we can exactly match the theoretical precision of the algorithm.
    A finite state machine is used to control the processing core.
    For a good comparison, the Matlab model it is also provided. The complete Verilog Modelsim testbench is generated according with options we made. For every function implemented we can check the output values and trajectories as well the relative errors to the Matlab model.
    The toolbox provides a fast way to check at once the silicon implementation of the designed CORDIC Processor.
    
    See also: CORDIC Matlab Toolbox
 
Features
Flexible architecture
Selectable quantization (TC) and no. of -rotations
Matlab model available
Testbench files generated acording with selections
Simulation results checked against Matlab model
One state machine to control the processing core
Plots using files generated by Verilog simulation
Synthesis Results*
Technology Inputs Arch. -rot. Gates  f [MHz]
ASIC - 0.25 m 16 bits (TC) Cascaded 15 12300 144
Recursive 15 2135 125
FPGA - Xilinx Virtex II 16 bits (TC) Cascaded 15 60% xc2v250 105
Recursive 15 34% xc2v80 91
*) all functions implemented
Test Results
 
Technical Support
 
support@icsdesign.com
Deliverables
Complete CORDIC RTL code generator (p-code)
Documentation
Price List
 
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